6. Code Docs¶
6.1. Normalizer-Module¶
6.2. Coverage-Module¶
6.3. Parser-Module¶
Parser for the execution trace file
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riscv_isac.parsers.
C_OPCODES
= {0: <function quad0>, 1: <function quad1>, 2: <function quad2>}¶ Instruction OP-CODES dict for 16-bit instructions
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riscv_isac.parsers.
OPCODES
= {3: <function load_ops>, 7: <function flw_fld>, 15: <function fence_ops>, 19: <function arithi_ops>, 23: <function auipc>, 27: <function rv64i_arithi_ops>, 35: <function store_ops>, 39: <function fsw_fsd>, 47: <function rv64_rv32_atomic_ops>, 51: <function arith_ops>, 55: <function lui>, 59: <function rv64i_arith_ops>, 67: <function fmadd>, 71: <function fmsub>, 75: <function fnmsub>, 79: <function fnmadd>, 83: <function rv32_rv64_float_ops>, 99: <function branch_ops>, 103: <function jalr>, 111: <function jal>, 115: <function control_ops>}¶ Instruction Op-Codes dict for 32-bit instructions
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riscv_isac.parsers.
extractAddress
(line, mode='standard')[source]¶ Function to extract the address from the line Check for the mode - spike or standard
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riscv_isac.parsers.
extractInstruction
(line, mode='standard')[source]¶ Function to extract the instruction code from the line Check for the mode - spike or standard
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riscv_isac.parsers.
extractOpcode
(instr)[source]¶ Function to extract the opcode from the instruction hex
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riscv_isac.parsers.
extractRegisterCommitVal
(line, mode)[source]¶ Function to extract the register commit value Only works for spike mode
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riscv_isac.parsers.
instr_pattern_c_sail_regt_reg_val
= re.compile('(?P<regt>[xf])(?P<reg>[\\d]+)\\s<-\\s(?P<val>[0-9xABCDEF]+)')¶ Regex pattern and functions for extracting instruction and address
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class
riscv_isac.parsers.
instructionObject
(instr_name, instr_addr, rd=None, rs1=None, rs2=None, rs3=None, imm=None, csr=None, shamt=None)[source]¶ Instruction object class
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__init__
(instr_name, instr_addr, rd=None, rs1=None, rs2=None, rs3=None, imm=None, csr=None, shamt=None)[source]¶ Constructor.
- Parameters
instr_name – name of instruction as accepted by a standard RISC-V assembler
instr_addr – pc value of the instruction
rd – tuple containing the register index and registerfile (x or f) that will be updated by this instruction
rs1 – typle containing the register index and registerfilr ( x or f) that will be used as the first source operand.
rs2 – typle containing the register index and registerfilr ( x or f) that will be used as the second source operand.
rs3 – typle containing the register index and registerfilr ( x or f) that will be used as the third source operand.
imm – immediate value, if any, used by the instruction
csr – csr index, if any, used by the instruction
shamt – shift amount, if any, used by the instruction
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__weakref__
¶ list of weak references to the object (if defined)
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riscv_isac.parsers.
parseCompressedInstruction
(input_line, mode, arch)[source]¶ Parse a compressed instruction Args: input_line - Line from the log file Returns: (instr_obj)
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riscv_isac.parsers.
parseInstruction
(input_line, mode, arch='rv32')[source]¶ Check if we are parsing compressed or normal instructions
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riscv_isac.parsers.
parseStandardInstruction
(input_line, mode, arch)[source]¶ Parse an input line and decode the instruction Args: input_line - Line from the log file Returns: (instr_name, rd, rs1, rs2, imm)
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riscv_isac.parsers.
quad0
(instr, addr, arch)[source]¶ Parse instructions from Quad0 of the Compressed extension in the RISCV-ISA-Standard